Use this page to discuss script 5494 vtags: verdi like, verilog code signal trace and show topo script
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Comments[]
Hi Caojun, I just find your vtags, it looks very good to trace verilog/systemverilog design. In the meanwhile I find one limitation in 3.00, if the verilog file is a link of designSync, vtags will throw out "RTL ERROR %d-%d: io not end with" error and skip this file. In my design env, most of the files are such link, Could you please help and fix this? Thanks, Xy Wang --July 22, 2019
- could you give me an simple example of your "link of designSync", and I will try to fix the issue. --4 October 2021
Hi cajun,
First of all, congratulations for becoming a father, blessings to your family :)
I am looking forward to try your script!